A phase-locked loop (PLL) generates an output clock that the PLL phase locks to an input reference clock. A digital PLL (DPLL) includes a time-to-digital converter (TDC) that generates a digital output value that is a function of the phase difference between corresponding edges of the reference dock and a feedback dock derived from the output dock. Based on the digital signal from the TDC, the output dock frequency from a voltage-controlled oscillator is adjusted to maintain phase lock.